1. Field of the Invention
The invention relates generally to methods and apparatus for maintaining the integrity of cache memory data in a computing system that includes a central processing unit (CPU) and associated cache memory, Random Access Memory (RAM), Read Only Memory (ROM), and a local memory controller for controlling cooperation between the CPU and the aforementioned memories. More particularly, the invention relates to methods and apparatus for maintaining cache integrity in a computer system, like the one described hereinabove, in which a ROM mapped to RAM mode of operation is supported, and a CPU write to ROM operation is performed while the ROM mapped to RAM mode is enabled.
2. Description of the Related Art
Well known computer systems, such as the IBM PS/2 Model 70 personal computing system, support mapping ROM to RAM to improve system operating speed. The terms IBM and IBM PS/2 are registered trademarks of INTERNATIONAL BUSINESS MACHINES CORPORATION.
It is also well known to perform "snoop" operations in computer systems which, as defined herein, are operations performed by a system device in an attempt to detect the presence (or alternatively the absence) of a predefined signal or set of signals. For example, in computer systems that include cache memory, snoop cycles have been implemented by local memory controllers to detect external write operations to main memory (e.g., a write being performed by an external bus master) involving data in a cache under the control of a particular memory controller. If such a write operation is detected during a local memory controller snoop cycle, a known response by the controller is to provide an invalidation signal and cache address signal to the local CPU so that the appropriate cache entry can be invalidated by the local CPU.
However, no computer system is known that (1) supports mapping ROM to RAM and (2) protects against data being destroyed in cache memory if a CPU write to ROM operation is performed when the aforesaid mapping is enabled. Although a write ROM operation will not be successful in modifying the contents of ROM; if ROM data is mapped to RAM and is cached on a fetch preceding a CPU write to ROM operation, the potential clearly exists for creating invalid cache data when the CPU write to ROM operation is performed. Such potential exists since each CPU is normally responsible for updating data in any cache memory associated with the processor, invalidating non current cache data values, etc.
Accordingly, it would be desirable if methods and apparatus were provided that would assure the integrity of data in cache memory whenever a CPU write to ROM operation is performed with ROM mapped to RAM. It would also be desirable if such methods and apparatus could be implemented using existing system components (memory controllers, CPUs, etc.) without introducing additional hardware into the computer system.
Furthermore, it would be desirable if the contemplated methods and apparatus performed the necessary functions to maintain cache integrity in parallel with the performance of the CPU write to ROM operation.
Still further, it would be desirable if a snoop cycle could be implemented in the memory controller responsible for cooperating with a given CPU, during which ROM write operations performed by the CPU (with ROM mapped to RAM) could be detected.
Further yet, it would be desirable if existing signalling protocols for invalidating cache entries (to maintain cache integrity) could be utilized in conjunction with the aforementioned snoop cycle for detecting CPU write to ROM operations, so that the overall design and the complexity of the computer system would not need to be changed in order to perform the desired cache invalidation procedure.